1. Field of the Invention
The present invention relates to a memory device having a self-test function using sense amplifiers, and more particularly to a memory device configured to simultaneously write data on all cells on one row of a matrix cell array constituting the memory device in a test mode, based on data latched in sense amplifiers included in the memory device, thereby reducing the test data write time. The present invention also relates to a method for controlling a data writing operation in a test mode of the above memory device.
2. Description of the Related Art
In accordance with conventional data writing techniques, data input to a memory device is written on only one cell of one bit designated by a selected row address and a selected column address.
A conventional data writing operation will now be described in conjunction with FIG. 1. Referring to FIG. 1, a RAM is illustrated which includes a sense amplification circuit configured to have common sense amplifiers.
As shown in FIG. 1, the RAM includes a first cell array block 1, a first selection unit 2 for selecting the first cell array block 1 in response to a first bit line isolation signal BISH, and a bit line pre-charge block 3 for pre-charging two bit lines constituting each bit line pair. The RAM also includes a second cell array block 4, a second selection unit 5 for selecting the second cell array block 4 in response to a second bit line isolation signal BISL, a sense amplifier block 6 for amplifying data output from the cell array blocks 1 and 4, and a sense amplifier pre-charge block 7 for pre-charging the sense amplifier block 6.
When the RAM having the above-mentioned configuration is to be written with data, one cell array block is first selected from the cell array blocks 1 and 4 included in the RAM in accordance with operations of the first and second selection units 2 and 5.
Thereafter, a cell to be written with one bit is selected from the selected cell array block, based on a row address strobe signal, a column address strobe signal, a row address signal and a column address signal. The data is then written in the selected cell via two bit lines associated therewith. After completing the data writing operation, the pre-charge block 3 is activated in response to a pre-charge signal BLP applied thereto. Simultaneously, a bit line pre-charge voltage signal vblp is applied to the pre-charge block 3. As a result, the bit lines are pre-charged with Vcc/2, namely, half the supply voltage.
At this time, the sense amplifier pre-charge block 7 is also activated, thereby pre-charging the sense amplifiers.
Consequently, the data written in the writing operation is erased, so that it cannot be used in the next writing operation. This means that it is necessary to input data in every writing operation.
Thus, the RAM operates in a limited fashion. In other words, upon testing a product such as the above-mentioned memory device, the number of data being read corresponds to the number of data being written. In order to achieve data writing for the entire cell of the cell array, it is necessary to sequentially carry out a data writing operation for one column of the cell array corresponding to a column address while addressing cells on the column by row addresses Xmin to Xmax, respectively, and then sequentially carry out the same data writing operation, as mentioned above, for the next column of the cell array corresponding to a column address incremented by one from the previous column address while addressing cells on the next column by row addresses Xmin to Xmax, respectively.
This operation is repeated for all columns of the cell array. In regard to data writing, there is no other method being more effective, except for a method using a page mode, which method may provide a more rapid writing operation.